Which Mips Register Is The Program Counter

Microprocessor Design

The Program Counter (PC) is a annals structure that contains the address arrow value of the electric current instruction. Each bike, the value at the pointer is read into the educational activity decoder and the plan counter is updated to indicate to the next instruction. For RISC computers updating the PC register is every bit simple as adding the machine discussion length (in bytes) to the PC. In a CISC machine, all the same, the length of the current pedagogy needs to exist calculated, and that length value needs to be added to the PC.

Updating the PC [edit | edit source]

The PC tin can exist updated by making the enable signal high. Subsequently each instruction bike the PC needs to be updated to point to the adjacent teaching in retentiveness. Information technology is important to know how the memory is arranged before constructing your PC update circuit.

Harvard-based systems tend to store one machine word per memory location. This means that every bike the PC needs to be incremented by 1. Computers that share data and instruction memory together typically are byte addressable, which is to say that each byte has its own accost, equally opposed to each machine give-and-take having its own address. In these situations, the PC needs to exist incremented by the number of bytes in the machine word.

In this image, the letter of the alphabet M is being used as the amount past which to update the PC each bicycle. This might be a variable in the case of a CISC machine.

Example: MIPS

The MIPS architecture uses a byte-addressable instruction memory unit. MIPS is a RISC reckoner, and that means that all the instructions are the same length: 32-bits. Every cycle, therefore, the PC needs to be incremented past 4 (32 bits = four bytes).

Instance: Intel IA32

The Intel IA32 (ameliorate known by some equally "x86") is a CISC compages, which means that each instruction can be a different length. The Intel memory is byte-addressable. Each cycle the educational activity decoder needs to make up one's mind the length of the instruction, in bytes, and it needs to output that value to the PC. The PC unit increments itself by the value received from the educational activity decoder.

Branching [edit | edit source]

Branching occurs at ane of a set of special instructions known collectively as "branch" or "jump" instructions

. In a branch or a jump, control is moved to a different didactics at a different location in pedagogy retentiveness.

During a branch, a new accost for the PC is loaded, typically from the instruction or from a register. This new value is loaded into the PC, and future instructions are loaded from that location.

Not-Offset Branching [edit | edit source]

A non-offset branch, oft referred to as a "leap" is a branch where the previous PC value is discarded and a new PC value is loaded from an external source.

In this prototype, the PC value is either loaded with an updated version of itself, or else it is loaded with a new Co-operative Address. For simplification nosotros practise not prove the control signals to the MUX.

Offset Branching [edit | edit source]

An offset branch is a branch where a value is added (or subtracted) to the current PC value to produce the new value. This is typically used in systems where the PC value is larger so a annals value or an immediate value, and it is non possible to load a consummate value into the PC. It is likewise commonly used to support relocatable binaries which may exist loaded at an arbitrary base of operations address.

In this image at that place is a second ALU unit. Observe that we could simplify this circuit and remove the second ALU unit of measurement if we use the configuration below:

These are merely 2 possible configurations for this circuit.

Starting time and Non-Offset Branching [edit | edit source]

Many systems have capabilities to use both beginning and not-showtime branching. Some systems may differentiate between the two equally "near jump" and "far jump" respectively, although this terminology is archaic.